1. Field
This disclosure is related to an output buffer and, more particularly, to an output buffer for an integrated circuit (IC) chip capable of interfacing to either one of a high and a low voltage bus or both.
2. Background Information
One problem that presents itself when coupling integrated circuit chips or IC's together is electrical compatibility. Typically, the integrated circuit chips are designed to operate at a particular input/output (I/O) voltage level or substantially within a particular restricted range of voltage levels. However, with advances in technology, the voltage levels at which integrated circuit chips operate, including for I/O, has been generally decreasing. Unfortunately, the trend for reducing voltages has been considerably faster for core logic, e.g., logic which does not interface to circuits outside the chip, than for I/O, e.g., circuits which primarily interface between chips. Consequently, recent ICs typically support I/O voltage levels which are higher than the core logic voltage levels. This allows for improved performance of the core independent of the support of legacy I/O voltage levels.
This general trend in the reduction of the I/O voltage levels may be an issue when designing or producing an integrated circuit chip. For example, an integrated circuit chip may be designed to operate with relatively high voltage signal levels. In this situation, the integrated circuit chip may not reach state-of-the-art performance levels, as measured by speed, power, and or both, for example, if designed to utilize high voltage tolerant transistors exclusively, although it will likely be compatible with legacy integrated circuit chips. Alternatively, the integrated circuit chip may operate at relatively low voltage levels and, therefore, be compatible with the voltage levels for state-of-the art integrated circuit chips, but may not be amenable to interfacing with legacy integrated circuit chips. For example, currently, but with no loss of generality, voltage levels of approximately 1.8 volts to approximately 3.3 volts may be considered relatively high, while voltage levels up to approximately 1 volt may be considered relatively low. It would be desirable if an approach or technique for producing or designing an integrated circuit chip provided the capability to address this issue.